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ADT7490
BIOS can read the THERM timer once an hour to
determine the cumulative THERM assertion time.
If, for example, the total THERM assertion time is
<22.76 ms in Hour 1, >182.08 ms in Hour 2, and
2.914 s
1.457 s
>2.914 sec in Hour 3, this indicates that system
performance is degrading significantly because
THERM is asserting more frequently on an hourly
basis.
2.914 s
1.457 s
THERM TIMER LIMIT
(REG. 0x7A)
728.32 ms
364.16 ms
182.08 ms
91.04 ms
45.52 ms
22.76 ms
0 1 2 3 4 5 6 7
7 6 5 4 3 2 1 0
728.32 ms
364.16 ms
182.08 ms
91.04 ms
45.52 ms
22.76 ms
THERM TIMER STATUS
(REG. 0x79)
THERM
THERM TIMER CLEARED ON READ
COMPARATOR
IN OUT
LATCH
RESET
CLEARED
ON READ
FAN4 BIT (BIT 5)
INTERRUPT STATUS 2
REGISTER
1 = MASK
FAN4 BIT (BIT 5)
SMBALERT
INTERRUPT MASK REGISTER 2
(REG. 0x75)
Figure 34. Functional Block Diagram of THERM Monitoring Circuitry
Alternatively, OS- or BIOS-level software can time-stamp
when the system is powered on. If an SMBALERT is
generated due to the THERM timer limit being exceeded,
another time-stamp can be taken. The difference in time can
be calculated for a fixed THERM timer limit time.
For example, if it takes one week for a THERM timer limit
of 2.914 sec to be exceeded, and the next time it takes only
1 hour, this is an indication of a serious degradation in system
performance.
Configuring the THERM Pin as an Output
In addition to monitoring T HERM as an input, the
ADT7490 can optionally drive THERM low as an output.
When PROCHOT is bidirectional, THERM can be used to
throttle the processor by asserting PROCHOT. The user can
preprogram system-critical thermal limits. If the
temperature exceeds a thermal limit by 0.25 ? C, THERM
asserts low. If the temperature is still above the thermal limit
on the next monitoring cycle, THERM stays low. THERM
remains asserted low until the temperature is equal to or
below the thermal limit. Because the temperature for that
channel is measured only once for every monitoring cycle,
after THERM asserts, it is guaranteed to remain low for at
least one monitoring cycle.
The THERM pin can be configured to assert low if the
Remote 1 THERM, local THERM, Remote 2 THERM or
PECI temperature limits are exceeded by 0.25 ? C. The
THERM temperature limit registers are at Register 0x6A,
Register 0x6B, and Register 0x6C, respectively. Setting
Bits [5:7 ] of Configuration Register 5 (0x7C) enables the
THERM output feature for the Remote 1, local, and
Remote 2 temperature channels, respectively. Figure 35
shows how the THERM pin asserts low as an output in the
event of a critical overtemperature.
THERM LIMIT
0.25 5 C
THERM LIMIT
TEMP
THERM
MONITORING
CYCLE
Figure 35. Asserting THERM as an Output, Based on
Tripping THERM Limits
An alternative method of disabling THERM is to program
the THERM temperature limit to –63 ? C or less in Offset 64
mode, or ? 128 ? C or less in twos complement mode; that is,
for THERM temperature limit values less than –63 ? C or
–128 ? C, respectively, THERM is disabled.
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